1. Field of the Art
The present invention relates to a sensing circuit unit for a dynamic circuit.
2. Background of the Art
Conventionally, there has been used a dynamic circuit as an arrangement of a large-scale circuit required to be operated at a high speed such as a register file, a RAM, a ROM, a PLA or the like. Such a dynamic circuit has a data line to be precharged to a predetermined voltage level, and uses a sensing circuit unit for detecting the voltage level of the data line.
A conventional sensing circuit unit for a register file reading circuit serving as a dynamic circuit will be discussed with reference to FIG. 14.
FIG. 14 shows a circuit diagram illustrating a conventional sensing circuit unit for a dynamic circuit.
In FIG. 14, a memory cell 701 in a register file comprises N-channel MOSFETs 701a, 701b and a latch circuit 701c. A precharge circuit 702 comprises a P-channel MOSFET. There is also an inverter circuit 703.
In the conventional sensing circuit unit for a dynamic circuit having the arrangement above-mentioned, when a precharge enable line 712 of the precharge circuit 702 is controlled so that the voltage level of a bit line 711 is precharged to a high voltage level (hereinafter referred to as "H") and a word line 713 of the memory cell 701 is set to "H", the voltage level of the bit line 711 is determined based on the contents of the memory cell 701.
When the contents of the memory cell 701 are "H", the bit line 711 is electrically discharged so that the voltage level of the bit line 711 is set to a low voltage level (hereinafter referred to as "L"). When the contents of the memory cell 701 are "L", the bit line 711 is not electrically discharged and no electric current flows therein. Accordingly, the bit line 711 remains "H". By the inverter circuit 703, a signal having a logic inverse to that of the voltage level of the bit line 711 is supplied to a sensing output line 714, so that the contents of the memory cell 701 are supplied.
In the conventional sensing circuit unit for a dynamic circuit having the arrangement above-mentioned, at the data reading time, the bit line 711 is electrically discharged only with the use of the MOSFETs 701a, 701b in the memory cell 701. Generally, to reduce a memory cell in area, the memory cell 701 uses the MOSFETs 701a, 701b of which gate widths are small. Further, these two MOSFETs are connected in series to each other. Accordingly, the electric discharge of the bit line 711 takes a long time. Particularly, in the application of a microprocessor or the like, each of the circuits is made in a large size, thus causing a data line such as the bit line 711 or the like to be lengthened. Further, a plurality of cells are connected to increase the wire resistance and load capacitance of the data line, causing the discharge time to be further increased.
As a result, the delay time between the time when the word line 713 is set to "H" and the time when the logic level of the sensing output line 714 is determined is increased. This disadvantageously increases the sensing time of the inverter circuit 703.